The present invention relates to a constant pulse width generator having applicability to a static random access memory.
The key desiderata in static random access memories (SRAMs) are speed, density, and power dissipation. Power dissipation is quite important, because there are typically important trade-offs between power and speed. That is, the high-current logic elements used to achieve high speed will normally imply high power dissipation, and power dissipation per unit area puts a grave limitation on density. Thus, any circuit architecture improvement which can generally reduce power dissipation will provide substantial advantages in the SRAM art.
Thus, it is an object of the present invention to provide a circuit architecture which reduces power dissipation in SRAM memories.
The use of a power down feature in high speed static RAMs introduced by intel in the 2147 4K.times.1 SRAM allowed the system to power up a few RAM chips on a memory board and fetch data from these chips while the rest were powered down. This allowed the duty cycle for the power dissipation to be small and therefore the average active power of the chip could be increased, thereby increasing the speed of the SRAM. Since the SRAM is asynchronous in operation, the chip select or enable signals were required to serve to initiate a read or write cycle with the currently valid address. Further improvement in sRAM access time was obtained by edge-triggered operations in the address path. This operation recognized a SRAM cycle to be asynchronous, and one that could be initiated by any address transition, if the chip was selected. The transition on any address line was detected and used to generate an internal clock to be used to precharge bit lines and allow sinse amplifiers to recover to the balanced state before the next cell was decoded. The use of this edge triggered (or "address transition bus" or "X-pulse") technique is quite widespread in many state-of-the-art SRAMs, serving the purpose described above.
This approach reduces the power consumption of a chip, and therefore higher-speed elements to be used without violating the contraints on average power dissipation per unit area averaged over the thermal relaxation time. However, even in this approach, elements are powered up for significant amounts of time when they are not actually in the signal path. For example, in a sample state-of-the-art SRAM technology, after an address transition (when the row and/or column address inputs provided at the external pins of the memory package change), it will typically take 2 to 5 ns for the address buffer to change state, 4 to 5 ns more for the row decoder to change state, and 4 to 5 additional ns before the past transistors in the row-selected memory cells in each column are open. Typically, another 15 to 20 ns will be required for the sense amplifier to change state. The column decoders require only 5 or 6 ns, after they have received the address, to raise a line connecting the sense amplifier of the selected column to the output buss. Thus, the sense amplifier is not actually in the signal path until 10 ns or so after the address buffer changes state. The column select logic is not actually in the single path until about 25 ns after the address buffer changes state. Moreover, the row decode logic is not in the signal path for more than about 10 or 15 ns after the address buffer has changed state. Thus, in the prior art all of these logic elements must be powered up during most of the read cycle, i.e., for 40 ns or more (until a first stage of the output buffer has changed state). This means that excessive power is being consumed. That is, each individual element in the signal path is being powered up for a total time which is much more than the time during which it is actually required to perform its function. While any individual element absorbs only a small amount of electrical energy during this excess power-up time, the net effect of this is that the total power dissipation of the peripheral elements is several times that required, and the average power dissipation of the SRAM (i.e., cell power dissipation plus peripheral power dissipation) is unnecessarily increased.
Thus, it is an object of the present invention to provide an SRAM wherein power dissipation in the peripheral circuits is minimized.
It is a further object of the present invention to provide an SRAM wherein the power dissipation in the peripheral circuits is not substantially larger than that strictly required for power-up of each circuit element during propagation of the signals.
The present invention differs from the conventional use of the address transition detection in the use of the clock to power up the signal propagation path synchronously with respect to the signal flow and in the use of the internal critical path timing elements to synchronize the power up times with the signal flow times, thereby reducing the active power dissipation cycle to the very minimum possible without degrading the speed of the SRAM. Since the timing elements used are identical for the signal and power path, they track each other over process variations and over temperature variations. In particular, dummy elements are used (such as dummy column address decoders) to provide the appropriate delays for the asynchronous power-up signals to activate the corresponding power elements, such as the actual column decoders. By this innovation, exact matching of the asynchronous signals to the appropriate delays needed to activate the power elements are perfectly tailored. That is, process variations which may cause changes in the propagation speed of logic elements will be mirrored by the propagation speed of the dummy elements so that the asynchronous power-up signals will still be provided to the actual power logic elements at the right time.
In the presently preferred embodiment, not only is the delay used to trigger the power-up input of each circuit element separately tailored for each circuit element, but also the duration of the power-up pulse provided each circuit element is also separately tailored. That is, a one-shot constant-width pulse generator is used to provide the power-upsignal to each circuit elements, and the width of the pulse provided by the one-shot pulse generator is also tailored.
According to the present invention, there is provided:
A constant pulse width generator comprising:
a first switch means for receiving an input signal having first and second logic states, said first switch means normally being disposed in an "on" state in response to the input signal being in the first logic state but changing to its "off" state when the input signal is in the second logic state;
output means for producing an output signal having first and second logic states;
first inverting delay means coupled to said output means for delaying said output signal produced therefrom and inverting the logic state of said output signal to produce an inverted output signal;
a second switch means alternatively disposable in "on" and "off" states, said second switch means being coupled to said first switch means and said output means and responsive to a predetermined condition of the delayed and inverted logic state of said output signal to operate in an inverted relation to the logic state of the output signal produced by said output means such that said second switch means is disposed in its "off" state after a delay when said output signal is in the first logic state and is disposed in its "on" state when said output signal is in the second logic state;
second inverting delay means coupled to the output of said first inverting delay means for providing a second delay of the output signal and inverting the logic state of said inverted output signal to return to the original logic state of the output signal; and
a third switch means alternatively disposable in "on" and "off" states, said third means being coupled to said output means and to a predetermined reference signal and responsive to the output of said second inverting delay means for imparting said reference signal to said output means when disposed in its "on" state, said reference signal corresponding to said second logic state;
said output means being thereby effective to produce a periodic pulse at the first logic state as the output signal having a width determined by the delay imparted by said first and second inverting delay means.
In another specific aspect of the present invention, there is provided:
A constant pulse width generator comprising:
a first field effect transistor having a gate for receiving an input signal alternatively assuming first and second logic state, said first field effect transistor being conductive when the input signal is in the first logic state and being non-conductive when the input signal is in the second logic state;
output means for producing an output signal having first and second logic states;
first inverting delay means coupled to said output means for delaying said output signal produced therefrom and inverting the logic state of said output signal to provide an inverted output signal;
a second field effect transistor having a gate and being coupled to said first field effect transistor and said output means;
a first feedback loop connected between the output of said first inverting delay means and the gate of said second field effect transistor;
said second field effect transistor being conductive when the inverted output signal from the output of said first inverting delay means is in the first logic state and being non-conductive when the inverted output signal is in the second logic state whereby the second field effect transistor is operable in an inverted relation to the logic state of the output signal produced by said output means;
second inverting delay means coupled to the output of said first inverting delay means for providing a second delay of the output signal and inverting the logic state of the inverted output signal to return to the original logic state of the output signal;
a third field effect transistor having a gate and being coupled to said output means and to a predetermined reference signal corresponding to the second logic state; and
a second feedback loop connected between the output of said second inverting delay means and the gate of said third field effect transistor;
said third field effect transistor being conductive when the output signal from the output of said second inverting delay means is in the first logic state and being non-conductive when the output signal from the output of said second inverting delay means is in the second logic state such that said output means is reset to the second logic state after a delay when said third field effect transistor is rendered conductive to impart said reference signal to said output means; and
said output means being thereby effective to produce a periodic pulse at the first logic state as the output signal having a width determined by the delay imparted by said first and second inverting delay means.